The present invention relates to a packet handler. More particulary the present invention relates to a packet handler of synchronous transfer mode (ATM) for fixed-length packets.
An ATM handler for transferring various information in fixed-length packets (hereinafter referred to as "cells"), as shown by reference numeral 1 in FIG. 2, for example, comprises a plurality of line interfaces (hereinafter referred to as the interface circuit) 3 for accommodating a plurality of transmission paths 2 (2-1 to 2-n') each including a pair of input and output lines, an ATM switch common part 4 including an ATM switch (ATM SW) 5 for distributing the input cells passed through each interface circuit 3 among the interface circuits in accordance with the routing information contained in the cell header, and a control part 9 connected to the interface circuits 3 and the ATM common switch part 4 through a control line 10.
Each interface circuit 3 includes the physical layer processing function for processing signals transmitted to and received from the transmission paths 2 in the physical layer, such as the photo-electric conversion in which the input light signal from an incoming line is converted into an electric signal and the electrooptic conversion of an output signal to an outgoing line, and the ATM layer processing function for processing signals for input and output cells in ATM layer, rewriting the header information (VPI/VCI) of the input cell into the header information for the output cell with reference to a header conversion table while at the same time such converting the header for adding the routing information required for the switching operation as the internal header information.
The control part 9 performs such operations as controlling the connections, rewriting the header conversion table information of each interface circuit 3 accompanying the setting/resetting the connection and collecting the various performance information acquired in each interface circuit 3 as well as the monitoring of the state of the ATM handler as a whole including the operation of the ATM switch common part 4. The control part 9 is linked with a network management function 13 via a communication line 12 to transmit various information to the network management function 13 in response to an order from the network management function 13 which is a higher level device of the control part 9.
In an ATM network requiring a high reliability like a public network, main transmission paths are made redundant in preparation for maintenance, inspection and detouring at the time of occurrence of a defect.
In employing a redundant transmission path, an interface circuit 3-i for accommodating one redundant transmission path 2-i (i=1 to n) is paired with an interface circuit 3-i' for accommodating the other transmission path 2-i'. One of the interface circuits is used as an active path, and the other as a standby path. The input cells from the interface circuits for active path are selected by a selector and input to an ATM switch 5. In such a case, as shown in FIG. 2, for example, a switching interface 6 including a selector 11 is provided for each pair of the interface circuits 3. In this way, only the input cells arriving from the interface circuits for an active path are led to input ports I (I-1 to I-n) of the ATM switch 5. The cells output from the output ports O (O-1 to O-n) of the ATM switch 5 are distributed between the two interface circuits of the pair at the switching interface 6.
Various forms of redundant architecture are available for transmission paths of a network.
FIG. 3 shows a network configuration in which a plurality of ATM handlers 1 are connected in mesh by a backbone network 2-b and each transmission path (backbone network) 2-b between the ATM handlers except for the subscriber lines 2-a are made redundant. On the other hand, FIG. 4 shows a network configuration in which a plurality of ATM handlers 1-a accommodating subscriber lines 2-a are bundled by ATM handlers 1-b as a backbone network. In this way, the number of backbone transmission paths for the ATM handlers 1-a at each terminal is reduced while the trunk line transmission paths 2-b are made redundant.
As seen from the above-mentioned two network configurations, the ATM handlers 1 desirably accommodate both the redundant transmission paths 2-b and the nonredundant transmission paths 2-a in any proportion ranging from the one in which all the lines accommodated are redundant to the one in which all the lines accommodated are nonredundant, as required.
In the system configuration shown in FIG. 2 comprising the selector 11 for each port I-i of the ATM switch 4 and a pair of the interface circuits 3 accommodating the redundant transmission path selectively connected through the selector 11 to the input port I-i, however, only one of the two interface circuits 3 can be effectively utilized in accommodating an independently-used nonredundant transmission path, with the result that the slots formed in the housing of the ATM handlers for accommodating the other one of the interface circuits 3 are wasted.
Also, in the ATM handlers shown in FIG. 2 which has a pair of interface circuits 3 for each input port of the ATM switch, the cell amount applicable to the ATM switch 5 remains constant regardless of whether the transmission paths accommodated are redundant or used independently. For the proportion of space that the interface circuit board occupies in the housing of the ATM handlers, therefore, the switching capability of the ATM switch 5 is low, thereby leading to the problem of the bulkiness of the system for the switching capacity.